Package memtest86+: Information
Source package: memtest86+
Version: 2.10-alt0.M41.1
Build time: Nov 20, 2008, 02:34 AM
Category: System/Kernel and hardware
Report package bugHome page: http://www.memtest.org
License: GPL
Summary: Memory test for x86 architecture
Description:
Memtest86 is thorough, standalone memory test for x86 systems. Memtest86 is a standalone program and can be loaded from either a disk partition via lilo or a floppy disk. Memtest86 uses a "moving inversions" algorithm that is proven to be effective in finding memory errors. The BIOS based memory test is just a quick check that will often miss many of the failures that are detected by Memtest86.
Maintainer: Michael Shigorin
Last changed
Nov. 20, 2008 Michael Shigorin 2.10-alt0.M41.1
- built for M41
Nov. 15, 2008 Michael Shigorin 2.10-alt1
- 2.10: + added support for: - Intel Core i7 (Nehalem), Atom CPU - Intel G41/G43/G45, P43/P45, US15W (Poulsbo) chipsets - Intel EP80579 (Tolapai) SoC CPU - ICH10 Southbridge (SPD/DMI) + added detection for Intel 5000X + added workaround for DDR3 DMI detection + now fully aware of CPU w/ L3 cache (Core i7 & K10) + fixed: - Intel 5000Z chipset detection - Memory Frequency on AMD K10 - cache detection on C7/Isaiah CPU - Memtest86+ not recognized as Linux Kernel - built with gcc 4.1 as upstream recommends for this version
March 29, 2008 Michael Shigorin 2.01-alt1
- 2.01: + added support for: - 45nm Mobile Core2 w/3Mb L2 - i945GM/PM/GME, i946PL/GZ, iGM965/iGL960/iPM965/iGME965/iGLE960 + added detection for: SiS 649/656/671/6, i430MX/i430TX + added an optional beep mode (pass completed w/o error) + pass duration 20% reduced + removed blinking cursor + reverted Test #0 to cached + fixed: - major bug in Memory Address Errors Reporting - Intel Mac - Intel 3-Series (P35/X38) chipset init - a bug with SPD Display and ESB6300 - a detection bug on P965/G965 C-Stepping - incoherency with pass progress indicator - Makefile to compile on x86_64 + bootable Memtest86+ ISO more compatible - 2.00 enhancements: + major architecture changes + modulo test now use random pattern for better accuracy + new Advanced DMI Errors Reporting Mode + added support for: - bus ratio changes on Intel Core CPU - non-integer bus ratio on latest Intel CPU - VIA C7/C7-D/C7-M/Eden on Esther Core - AMD K10 (Phenom) CPU w/timings detection - Intel Pentium E w/1 MB L2 Cache - Intel Core2 45nm (Penryn) - FSB1333/FSB1600 Intel CPU - Intel 5400A/5400B, Q35/P35/G33/Q33, X38/X48 w/timings detection + added preliminary support for: + VIA CN Isaiah CPU, Intel Nehalem + Intel 5000P/V/Z + added SPD Data Display for all Intel Chipsets (more to come) + added serial support as a linux boot parameter (Thanks to Michal S.) + removed on-the-fly memory timings change (unstable) + numerous (really) bug fixes