Package verilator: Information

Source package: verilator

Version: 3.924-alt1

Build time:  Jun 22, 2018, 06:15 AM in the task #208829

Category: Engineering

Gear: https://git.altlinux.org/gears/v/verilator.git?a=tree;hb=9fce891…

Home page: https://www.veripool.org/wiki/verilator

License: LGPLv3 or Perl Artistic 2.0

Summary: A fast and free Verilog HDL simulator

Description: 

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.

List of RPM packages built from this SRPM:
verilator (x86_64, i586, aarch64)
verilator-debuginfo (x86_64, i586, aarch64)
verilator-doc (noarch)

Maintainer: Elvira Khabirova