Package verilator: Information

Source package: verilator

Version: 4.226-alt1

Build time:  Sep 15, 2022, 09:30 PM in the task #306321

Category: Engineering

Gear: https://git.altlinux.org/gears/v/verilator.git?a=tree;hb=716362e…

Home page: https://www.veripool.org/wiki/verilator

License: LGPLv3 or Artistic-2.0

Summary: A fast and free Verilog HDL simulator

Description: 

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.

List of rpms provided by this srpm:
verilator (x86_64, ppc64le, i586, aarch64)
verilator-debuginfo (x86_64, ppc64le, i586, aarch64)
verilator-doc (noarch)

Maintainer: Egor Ignatov