Package iverilog: Information

    Source package: iverilog
    Version: 12.0-alt1
    Build time:  Jun 27, 2023, 09:46 AM
    Category: Engineering
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    License: GPLv2
    Summary: Verilog simulation and synthesis tool
    Description: 
    Icarus Verilog is a Verilog simulation and synthesis tool. It operates
    as a compiler, compiling source code written in Verilog (IEEE-1364)
    into some target format. For batch simulation, the compiler can generate
    an intermediate form called vvp assembly. This intermediate form is
    executed by the ``vvp'' command. For synthesis, the compiler generates
    netlists in the desired format. It supports the 1995, 2001 and 2005
    versions of the standard, portions of SystemVerilog, and some extensions.

    List of RPM packages built from this SRPM:
    iverilog (e2kv6, e2kv5, e2kv4, e2k)
    iverilog-debuginfo (e2kv6, e2kv5, e2kv4, e2k)

    Maintainer: Egor Ignatov

    List of contributors:
    Egor Ignatov
    Elvira Khabirova

      1. gcc-c++
      2. /proc
      3. bzip2-devel
      4. libreadline-devel
      5. gperf
      6. flex
      7. zlib-devel

    Last changed


    Jan. 10, 2023 Egor Ignatov 12.0-alt1
    - 12.0
    Aug. 25, 2021 Egor Ignatov 11.0-alt3
    - add -ffat-lto-objects to build static libs with -flto enabled
    April 29, 2021 Egor Ignatov 11.0-alt2
    - Add bzip2 and zlib build dependencies (Closes: #37929)