Package verilator: Information
Binary package: verilator
Version: 3.924-alt1
Architecture: ppc64le
Build time: May 24, 2019, 04:11 PM
Source package: verilator
Category: Engineering
Report package bugDownload: verilator-3.924-alt1.ppc64le.rpm
Home page: https://www.veripool.org/wiki/verilator
Summary: A fast and free Verilog HDL simulator
Description:
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
Maintainer: Elvira Khabirova