Package arachne-pnr: Information
Source package: arachne-pnr
Version: 0.1.0.0.310.g5d830dd-alt1
Build time: Jun 22, 2018, 05:00 AM in the task #208826
Category: Engineering
Report package bugHome page: https://github.com/cseed/arachne-pnr
License: MIT/X Consortium
Summary: Place and route tool for iCE40 family FPGAs
Description:
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a harware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.
List of RPM packages built from this SRPM:
arachne-pnr (x86_64, i586, aarch64)
arachne-pnr-chipdb (noarch)
arachne-pnr-debuginfo (x86_64, i586, aarch64)
arachne-pnr (x86_64, i586, aarch64)
arachne-pnr-chipdb (noarch)
arachne-pnr-debuginfo (x86_64, i586, aarch64)
Maintainer: Elvira Khabirova
Last changed
June 22, 2018 Elvira Khabirova 0.1.0.0.310.g5d830dd-alt1
- New version - Move noarch chipdb files to a separate package
July 16, 2017 Elvira Khabirova 0.1.0.0.203.g7e135ed-alt1
- New version
Jan. 23, 2017 Elvira Khabirova 0.0.0.187.e97e35c-alt1
- Initial build