Package iverilog: Information

Source package: iverilog

Version: 10.2-alt1

Build time:  Jun 22, 2018, 06:15 AM in the task #208829

Category: Engineering

Gear: https://git.altlinux.org/gears/i/iverilog.git?a=tree;hb=87ffd514…

Home page: http://iverilog.icarus.com

License: LGPLv2.1

Summary: Verilog simulation and synthesis tool

Description: 

Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.

List of rpms provided by this srpm:
iverilog (x86_64, i586, aarch64)
iverilog-debuginfo (x86_64, i586, aarch64)

Maintainer: Elvira Khabirova