Package verilator: Information
Binary package: verilator
Version: 5.018-alt1
Architecture: ppc64le
Build time: Nov 24, 2023, 06:21 PM in the task #335057
Source package: verilator
Category: Engineering
Report package bugDownload: verilator-5.018-alt1.ppc64le.rpm
Home page: https://www.veripool.org/wiki/verilator
License: LGPLv3 or Artistic-2.0
Summary: A fast and free Verilog HDL simulator
Description:
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
Maintainer: Egor Ignatov
Last changed
Nov. 24, 2023 Egor Ignatov 5.018-alt1
- new version 5.018
July 22, 2023 Ilya Kurdyukov 5.012-alt1.1
- fixed build for Elbrus
July 19, 2023 Egor Ignatov 5.012-alt1
- new version 5.012