Package verilator: Information
Default inline alert: Version in the repository: 5.018-alt1
Source package: verilator
Version: 4.212-alt1
Build time: Sep 16, 2021, 02:14 PM in the task #285105
Category: Engineering
Report package bugHome page: https://www.veripool.org/wiki/verilator
Summary: A fast and free Verilog HDL simulator
Description:
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
List of rpms provided by this srpm:
verilator (x86_64, ppc64le, i586, armh, aarch64)
verilator-debuginfo (x86_64, ppc64le, i586, armh, aarch64)
verilator-doc (noarch)
verilator (x86_64, ppc64le, i586, armh, aarch64)
verilator-debuginfo (x86_64, ppc64le, i586, armh, aarch64)
verilator-doc (noarch)
Maintainer: Egor Ignatov
Last changed
Sept. 13, 2021 Egor Ignatov 4.212-alt1
- new version 4.212
July 9, 2021 Egor Ignatov 4.210-alt1
- new version 4.210 - remove 0001-Fix-V3Hash-when-building-m32 patch
June 21, 2021 Egor Ignatov 4.204-alt1
- new version - add patch to fix build on 32 bit systems - documentation format changed