Package verilator

Source package: verilator
Version: 4.222-alt1
Build time:  May 6, 2022, 06:12 PM
 in the task #299560
Category: Engineering
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License:  LGPLv3 or Artistic-2.0
Summary:  A fast and free Verilog HDL simulator
Description: 
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.
List of rpms provided by this srpm: 
verilator (x86_64, ppc64le, i586, aarch64)
verilator-debuginfo (x86_64, ppc64le, i586, aarch64)
verilator-doc (noarch)
Last changes:
May 6, 2022 Egor Ignatov 4.222-alt1
- new version 4.222
March 17, 2022 Egor Ignatov 4.220-alt1
- new version 4.220
Jan. 21, 2022 Egor Ignatov 4.218-alt1
- new version 4.218

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