Package iverilog: Information

Binary package: iverilog

Version: 12.0-alt1

Architecture: loongarch64

Build time:  Oct 21, 2023, 11:36 AM

Source package: iverilog

Category: Engineering

Download: iverilog-12.0-alt1.loongarch64.rpm

Home page: http://iverilog.icarus.com

License: GPLv2

Summary: Verilog simulation and synthesis tool

Description: 

Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.

Maintainer: Egor Ignatov